Hardware facilities are described whereby the processors of task dispatching, preemption, enqueuing and dequeuing may be handled in a manner which is faster, uses less storage and is less prone to error in programming. A task is herein defined as a section of executable code which has been provided with a controlled environment in which to execute. This controlled environment commonly includes a complete set of status associated with the task. This status may include instruction address, register contents, and sundry control information relating to the execution status of the task. It has been common in previous computer systems to have this information grouped together only by software concept. That is to say, the task management software retains in main storage a block of data defining the parameters mentioned above but the hardware does not regard this as a unit of task control; rather individual instructions are provided whereby, for instance, registers may be loaded, the instruction address may be loaded and certain control information may be set up. Since this entire block of information must be changed every time the current task is changed, this process becomes very time consuming. In addition, the large number of instructions required to handle each piece of information separately, lead to the use of large amounts of storage to manage the transfer of information and also allow opportunities for errors in programming.